About this document
SDC Eamples by Amar Vishwakarma is a document available to read on EtoBox.
The document provides an overview of Synopsys Design Constraints (SDC) used in VLSI design, detailing its syntax, key commands, and constraints related to timing, power, and area. It outlines various important constraints such as SDC version, units, driving cells, load settings, timing constraints, and exceptions like multicycle and false paths. The SDC file format is based on TCL syntax and is widely supported across synthesis and place-and-route tools.
- Author
- Amar Vishwakarma
- Language
- EN