About this document
Pulsed Latch Power Reduction Techniques by hari is a document available to read on EtoBox.
1) The document discusses replacing flip-flops with pulsed latches to reduce power consumption while meeting timing constraints. Pulsed latches have lower power and area than flip-flops. 2) It presents an approach for pulsed latch replacement that utilizes the intrinsic time borrowing property of pulsed latches to find feasible regions that satisfy timing even when delays change due to the replacement. 3) Experimental results show the approach can effectively reduce clock power consumed by sequencing ele
- Author
- hari
- Language
- EN