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Implementation of High Speed FFT Core For Low Power Hardware Without Using ROM For Twiddle Factor Storage by Sathi Dinesh Reddy is a document available to read on EtoBox.

What is Implementation of High Speed FFT Core For Low Power Hardware Without Using ROM For Twiddle Factor Storage about?

FFT is an efficient algorithm to calculate Discrete Fourier Transform (DFT) and its inverse. The proposed design implements a radix-4 FFT processor, which incorporates a low power commutator and a Butterfly structure without a multiplier. The parallel pipe lined architecture of the processor also has higher throughput with lowered power consumption.

Author

Sathi Dinesh Reddy

Language

EN