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Power Delivery for Three-Dimensional ICs by Pavlidis, Vasilis F. ;Savidis, Ioannis ;Friedman, Eby G. is a scholarly article available to read on EtoBox.

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4.5.3.3 Per Cent variation in capacitance -- 4.5.3.4 Per Cent variation in coupling capacitance -- 4.5.4 Compact Conductance Model of a Three-Dimensional Via -- 4.5.4.1 Compact models of through silicon via conductance -- 4.6 Electrical Characterization Through Numerical Simulation -- 4.6.1 Ansys Quick Three-Dimensional Electromagnetic Field Solver -- 4.6.2 Numerical Analysis of Through Silicon Via Impedance -- 4.7 Case Study-Through Silicon Via Characterization of the MITLL TSV process -- 4.7.1 MIT Lincoln Laboratory Three-Dimensional Process -- 4.7.2 RLC Extraction of a Single Three-Dimensional Via -- 4.7.3 RLC Coupling Between Two Three-Dimensional Vias -- 4.7.4 Effects of Three-Dimensional Via Placement on Shielding -- 4.7.5 Effect of the Return Path on Three-Dimensional Via Inductance -- 4.8 Summary -- 5 Substrate Noise Coupling in Heterogeneous Three-Dimensional ICs -- 5.1 Heterogeneous Substrate Coupling -- 5.1.1 Common Circuits and Compatible Substrate Types -- 5.1.2 Resistive Properties of Different Substrate Materials -- 5.1.3 Noise Model Reduction for Different Substrate Materials -- 5.2 Frequency Response -- 5.2.1 Isolation Efficiency of Noise Coupled System -- 5.2.2 Tr

Author

Pavlidis, Vasilis F. ;Savidis, Ioannis ;Friedman, Eby G.

Publisher

Morgan Kaufmann is an imprint of Elsevier

Published

2017

Language

EN

ISBN

9780124104846