About this document
VHDL Code for 4-Bit Shift Register by Darshan Patel is a document available to read on EtoBox.
The document describes a 4-bit shift register implemented in VHDL. It contains the VHDL code for an entity with ports for a clock, load, write, and 4-bit input and output. The behavioral architecture contains a process that shifts the input left by 1 bit on each clock edge when load is high, and loads the write value into the least significant bit. The output is assigned the shifted value.
- Author
- Darshan Patel
- Language
- EN