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Formal Methods for the Verification of Digital Circuits by Van Eijk C.A.J. is a nonfiction available to read on EtoBox.
What is Formal Methods for the Verification of Digital Circuits about?
Диссертация, Technische Universiteit Eindhoven, 1997, -156 pp. With the increasing complexity and tight time-to-market schedules of today’s digital systems, it is becoming more and more difficult to design correct circuits for these systems. Therefore, throughout the design process it is necessary to check that no errors are made. This task is called verification. Traditionally, a design is verified by simulating it extensively. This approach is no longer adequate, because it is too time-consuming and it gives no absolute guarantees about the correctness of the design. One of the approaches that have been put forward to solve these problems is formal verification. The key characteristic of this approach is that formal methods are applied to actually construct a mathematical proof for the correctness of the design. In this thesis, we discuss formal methods for the verification of synchronous digital circuits. More specifically, we describe methods to verify the functional equivalence of circuits specified at the register transfer and gate level. Such methods can be used in practice to verify that the circuit descriptions preceding and following a design step define the same functio
Who reads Formal Methods for the Verification of Digital Circuits?
It is typically read by self-directed learners exploring a subject in depth.
Common subject areas: history, science, philosophy, social sciences.
- Author
- Van Eijk C.A.J.
- Publisher
- Technische Universiteit Eindhoven
- Published
- 1997
- Language
- EN
- ISBN
- 9789038603704
- Category
- nonfiction
- Subjects
- Mathematics, Discrete Mathematics, Stem