About this document
I2C Core Verification with UVM and SV by DaZzling Sâwâň is a document available to read on EtoBox.
The document discusses the functional verification of an I2C Master Core using SystemVerilog and the Universal Verification Methodology (UVM). It compares the two verification environments, highlighting that both achieved high assertion coverage, with SystemVerilog yielding slightly better functional coverage. The paper emphasizes the importance of structured verification methodologies in improving communication and reusability in the verification process.
- Author
- DaZzling Sâwâň
- Language
- EN