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Delay and Peak Power Minimization for On-chip Buses Using Temporal Redundancy by K. Najeeb; Vishal Gupta; V. Kamakoti is a scholarly article available to read on EtoBox.

What is Delay and Peak Power Minimization for On-chip Buses Using Temporal Redundancy about?

In this paper, we propose a novel temporal redundancy based encoding technique for delay and peak power minimization. The proposed encoding scheme is tested with the SPEC2000 CINT benchmarks for 90nm and 65nm technologies. The experimental results show that our approach is very effective in reducing the peak power. From the delay perspective, our approach reduces the delay by at least 11% (4%) in the address (data) buses compared to the data transmission without encoding.

Author

K. Najeeb; Vishal Gupta; V. Kamakoti

Publisher

ACM

Published

2006

Language

EN