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VLSI CMOS Gate Design with Mentor Graphics by Akshit Jain is a document available to read on EtoBox.

What is VLSI CMOS Gate Design with Mentor Graphics about?

The document is an assignment submitted by Akshit Jain to their professor for their EE-404: Digital VLSI course at the University of Bridgeport. The assignment asks students to design, simulate, and create layouts for NAND, NOR, EXOR and EXNOR CMOS gates using Mentor Graphics tools. For each gate, the student provides the schematic from Design Architect, simulation results from Accusim, and the layout from IC Station, along with layout vs schematic reports.

Author

Akshit Jain

Language

EN