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DLD Through Verilog by rowdysanthu02 is a document available to read on EtoBox.
What is DLD Through Verilog about?
The document is a laboratory manual for the DLD through Verilog course (EC-410) prepared by M. Yuvapriya, an Assistant Professor in the Department of Electronics & Communication Engineering at Gokulakrishna College of Engineering. It includes a list of experiments such as basic logic gates, half and full adders, and half and full subtractors. The college is approved by AICTE and affiliated with JNTUA.
- Author
- rowdysanthu02
- Language
- EN