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A Comprehensive Test Pattern Generation Approach Exploiting the SAT Attack for Logic Locking by Yadi Zhong; Ujjwal Guin is a Computer Science article available to read on EtoBox.

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The need for reducing manufacturing defect escape in today's safety-critical applications requires increased fault coverage. However, generating a test set using commercial automatic test pattern generation (ATPG) tools that lead to zerodefect escape is still an open problem. It is challenging to detect all stuck-at faults to reach 100% fault coverage. In parallel, the hardware security community has been actively involved in developing solutions for logic locking to prevent IP piracy. In logic locking, locks are inserted in different locations of the netlist to modify the original functionality. Unless the correct key is programmed into the IC, the circuit functions incorrectly. Unfortunately, the Boolean satisfiability (SAT) based attack, introduced in [1], can determine the secret key efficiently, and break different logic locking schemes. In this paper, we propose a novel test pattern generation approach using the powerful SAT attack on logic locking. A stuck-at fault is modeled as a locked gate with a secret key, where it can effectively deduce the satisfiable assignment with reduced backtracks under key initialization of the SAT attack. The input pattern that determines the k

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Author

Yadi Zhong; Ujjwal Guin

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Published

2023

Language

EN

Field

Computer Science (Physical Sciences)