About this document
Scan Chain Insertion in VLSI Design by senthilkumar is a document available to read on EtoBox.
This document describes observations from a scan insertion lab experiment. The design had 1 clock domain and contained 2 memories but no memory BIST or collars. Scan insertion added 2 scan chains, with chain lengths of 39 and 38, to address S7 violations and undefined modules. A total of 77 scan flops were added. The top-down scan insertion approach added no lockup latches.
- Author
- senthilkumar
- Language
- EN