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Fault Resilient Physical Neural Networks on a Single Chip by Weidong Shi; Yuanfeng Wen; Ziyi Liu; Xi Zhao; Dainis Boumber; Ricardo Vilalta; Lei Xu is a scholarly article available to read on EtoBox.

What is Fault Resilient Physical Neural Networks on a Single Chip about?

Device scaling engineering is facing major challenges in producing reliable transistors for future electronic technologies. With shrinking device sizes, the total circuit sensitivity to both permanent and transient faults has increased significantly. Research for fault tolerant processors has primarily focused on the conventional processor architectures. Neural network computing has been employed to solve a wide range of problems. This paper presents a design and implementation of a physical neural network that is resilient to permanent hardware faults. To achieve scalability, it uses tiled neuron clusters where neuron outputs are efficiently forwarded to the target neurons using source based spanning tree routing. To achieve fault resilience in the face of increasing number of permanent hardware failures, the design proactively preserves neural network computing performance by selectively replicating performance critical neurons. Furthermore, the paper presents a spanning tree recovery solution that mitigates disruption to distribution of neuron outputs caused by failed neuron clusters. The proposed neuron cluster design is implemented in Verilog. We studied the fault resilience p

Author

Weidong Shi; Yuanfeng Wen; Ziyi Liu; Xi Zhao; Dainis Boumber; Ricardo Vilalta; Lei Xu

Publisher

ACM

Published

2014

Language

EN