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The document describes a proposed low power VLSI architecture for classifying arrhythmic heartbeats using a deep neural network. It aims to provide accurate arrhythmia classification in a power optimized design suitable for wearable devices. The proposed methodology achieves 97.01% accuracy and 99.09% specificity on the MIT-BIH dataset, comparable or better than other algorithms implemented in software or ASIC platforms. The design is realized at 180nm CMOS technology with low power consumption of 6.82x les

Author

Vaishnavi Pandurangan

Language

EN