About this document

Digital Systems Design Lab Overview by aryansinghsikarwar123 is a document available to read on EtoBox.

The document outlines the Digital Systems Design Lab course (BECE102P) led by Dr. Dilip Kumar Choudhary at Vellore Institute of Technology. It includes a ModelSim software download link, assessment rubrics, and specific tasks for students, such as writing Verilog models for logic gates and half adder/subtractor. Additionally, it provides examples of Verilog HDL code and test benches for practical implementation.

Author

aryansinghsikarwar123

Language

EN