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Aishwarya Hiremath: Design Verification Expert by Jalaj Gupta is a document available to read on EtoBox.

What is Aishwarya Hiremath: Design Verification Expert about?

This document is a resume for Aishwarya Hiremath. It summarizes her professional experience in design verification over 4.5 years, including roles at Marvell Semiconductors, Cyient Ltd, and Karmic Design Pvt Ltd verifying IPs such as network IPs, memory IO, power management, and protocols like AMBA APB and Q-channel expander. It also lists her education including a Master

Author

Jalaj Gupta

Language

EN