About this document
Understanding Wire Load Models in VLSI by Renju Tj is a document available to read on EtoBox.
WLM is an estimation of delay based on area and fanout that is used prior to routing. It estimates interconnect length and capacitance based on statistics from previously routed chips. WLM provides tables of net fanout versus load, resistance, and area to estimate interconnect delays during compilation when actual parasitic values are unknown. After physical synthesis, WLM is no longer used.
- Author
- Renju Tj
- Language
- EN