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This paper presents a low-power, low-noise dynamic comparator utilizing a latch-embedding floating amplifier (LEFA) designed for energy efficiency and high-speed performance in analog-to-digital converters (ADCs). Simulated in 28-nm CMOS technology, the comparator achieves a maximum clock frequency of 1.8 GHz with only 0.7 pJ per comparison and improved noise performance compared to previous designs. The proposed architecture enhances delay time and energy efficiency, making it suitable for high-speed SAR A

Author

harshavrdhan18

Language

EN