About this scholarly article

2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers. - The 65nm 16MB On-Die L3 Cache for a Dual Core Multi-Threaded Xeon/sup ~/ Processor by Chang, J.; Huang, M.; Shoemaker, J.; Benoit, J.; Chen, S.-L.; Chen, W.; Chiu, S.; Ganesan, R.; Leong, G.; Lukka, V.; Rusu, S.; Srivastava, D. is a scholarly article available to read on EtoBox.

Author

Chang, J.; Huang, M.; Shoemaker, J.; Benoit, J.; Chen, S.-L.; Chen, W.; Chiu, S.; Ganesan, R.; Leong, G.; Lukka, V.; Rusu, S.; Srivastava, D.

Publisher

IEEE

Published

2006

Language

EN