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This paper presents a design for a 13-bit fully parallel two-step single slope ADC aimed at enhancing the performance of high-speed CMOS image sensors. The proposed ADC achieves a conversion time of 512 ns while maintaining low power consumption of 47 μW, making it suitable for hundreds of megapixel applications. The design addresses the challenges of speed, accuracy, and integration, ultimately improving the frame rate for high-resolution image capture.

Author

vathsala s

Language

EN