About this document
Minimizing Leakage in CMOS VLSI by Shiksha Singh is a document available to read on EtoBox.
The document proposes a circuit to minimize leakage current in CMOS circuits during standby mode. It does this by determining the optimal reverse body bias voltage that balances subthreshold and band-to-band tunneling leakage currents, which vary differently with bias. Simulation results on a 32nm technology show up to 1,491x standby leakage power reduction compared to no body bias. Additionally, the circuit compensates for process, voltage, and temperature variations using feedback to maintain low leakage
- Author
- Shiksha Singh
- Language
- EN