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Low-Power 2-Stage Clock Multiplier Design by hspark is a document available to read on EtoBox.

This document presents a low-power, low-jitter two-stage clock multiplier designed in a 65 nm CMOS process, operating between 2.46–4.92 GHz. The architecture utilizes a delay-locked loop and edge combiner to achieve an 8× multiplication in the first stage, followed by a high-frequency oscillator in the second stage for a total multiplication factor of 64–128. The design focuses on minimizing output jitter while maintaining low power consumption, achieving integrated jitter values of 761 fsrms and 825 fsrms

Author

hspark

Language

EN