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What is Null Convention Logic Exponent Adder Design about?

This paper presents the design and implementation of an 8-bit exponent adder using Null Convention Logic (NCL) to enhance power efficiency during floating-point multiplication. The proposed NCL adder demonstrates a 39% reduction in power consumption compared to its synchronous counterpart, albeit with a 26.9% increase in area. The design was simulated using VHDL and transistor-level implementations, highlighting the advantages of asynchronous design paradigms in modern semiconductor applications.

Author

toilt

Language

EN