About this document
Structural Modeling in Verilog by enzuek is a document available to read on EtoBox.
This document provides an overview of a course on VLSI system design. It outlines the objectives of structural modeling, including describing gate primitives, modeling designs using gates, and specifying delays in gates. It then provides examples of modeling basic logic gates, a full adder, and a multiplexer using structural modeling in Verilog. It also discusses instantiating modules to represent hierarchy, connecting modules, and the effects of inertial and transport delays.
- Author
- enzuek
- Language
- EN