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Optimizing Logical Effort in VLSI Design by Nikhil Kumar Jaiswal is a document available to read on EtoBox.
The document discusses logical effort, a method for estimating delays in logic networks. It can help designers choose the best circuit topology, number of stages, and transistor widths. Logical effort uses a simple delay model and allows for back-of-the-envelope calculations. Delay has two components - effort delay, which depends on logical effort and electrical effort, and parasitic delay. Logical effort is calculated from delay versus fanout plots or by comparing transistor widths and represents the relat
- Author
- Nikhil Kumar Jaiswal
- Language
- EN