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This document outlines two lab session tasks for an electrical engineering class on digital system design. Students are asked to design and verify 8-bit and 12-bit adders using different approaches, including carry look ahead, carry select, and conditional sum. They must write Verilog code and estimate the area and delay of each design in terms of logic gates. Students will be evaluated on their programming skills, logical development, and engineering practice based on specified course learning outcomes.

Author

Zeeshan Ali

Language

EN