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Delay Estimation in VLSI Design by Yash Gupta is a document available to read on EtoBox.
What is Delay Estimation in VLSI Design about?
1) Transistor sizing techniques can be used to equalize the propagation delays of gates to minimize the delay through a combinational path. 2) Logical effort and electrical effort models allow estimating the propagation delay of a gate and analyzing the delay of a combinational network. 3) Various techniques like progressive transistor sizing, input reordering, and logic restructuring can be applied to optimize the delay of a combinational circuit.
- Author
- Yash Gupta
- Language
- EN