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This document describes the design of a two-stage CMOS operational amplifier in 180nm technology. It presents the circuit design and discusses its key performance parameters and simulation results. The operational amplifier provides a gain of 63dB and a bandwidth of 140 kHz for a 1pF load. It has a common mode gain of -25dB, an output slew rate of 32V/μs, and operates from a 1.8V power supply while consuming 300μW of power. The document analyzes the theoretical operation of the circuit and discusses how its

Author

Suyog Dhakne

Language

EN