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What is Power Optimization in CMOS Circuits about?

This project proposes a linear programming approach to optimize static power in digital CMOS circuits. It aims to minimize leakage power through fine-grained sleep transistor placement and sizing while satisfying delay constraints. Key aspects include developing relationships between sleep transistor sizing, gate delay, and leakage. The problem is formulated as a linear program to be solved efficiently. Experimental results will show the effectiveness of the linear programming formulation in optimizing leak

Author

Satish Babu Bodakunta

Language

EN