Opening book details…
About this Engineering article
Modeling for reduced gate capacitance of nanoscale MOSFETs by Dai Yue-hua; Chen Jun-ning; Ke Dao-ming; Xu Chao; Sun Jia-e is a Engineering article available to read on EtoBox.
It is typically read by researchers, students, and practitioners in Engineering.
- Author
- Dai Yue-hua; Chen Jun-ning; Ke Dao-ming; Xu Chao; Sun Jia-e
- Publisher
- Elsevier Science; Elsevier ; Elsevier Ltd.; Elsevier BV (ISSN 0038-1101)
- Published
- 2006
- Field
- Engineering (Physical Sciences)
More by Dai Yue-hua; Chen Jun-ning; Ke Dao-ming; Xu Chao; Sun Jia-e
Browse all works by Dai Yue-hua; Chen Jun-ning; Ke Dao-ming; Xu Chao; Sun Jia-e