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This document contains slides from a lecture on combinational circuits. It discusses topics like bubble pushing, compound gates, logical effort analysis and designing multiplexers using different gate styles. Examples are provided to sketch multiplexer designs using AND/OR/NAND/NOR gates and compound gates. Logical effort and delay calculations are performed to estimate the delay of NAND and compound gate based multiplexer designs driving a load of 160 units from inputs of 16 units each. The slides conclude

Author

Abhishek Bhardwaj

Language

EN