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SRAM ECC for Adjacent Bit Error Correction by swapnakoppula678 is a document available to read on EtoBox.

What is SRAM ECC for Adjacent Bit Error Correction about?

This document discusses improving SRAM reliability using error correcting codes (ECC) to detect and correct multiple adjacent bit errors. It proposes new ECC codes that can detect and correct adjacent 2-bit errors and detect adjacent 3-bit errors using the same number of parity bits as existing SEC-DED codes, reducing hardware overhead.

Author

swapnakoppula678

Language

EN