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What is LUT Optimization for ASIC Design Flow about?

This document proposes a new LUT-based optimization flow tailored for ASIC synthesis rather than FPGAs. It enhances LUT mapping to consider literal costs and extends Boolean methods to simplify LUT networks targeting the best implementation after decomposition. The techniques improve 12 area results from an EPFL benchmark suite. When embedded in a commercial EDA tool, the LUT optimization reduces area by 1.80%, total negative slack by 0.39%, and switching power by 1.72% after physical implementation, with a

Author

cs Tian

Language

EN