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This document summarizes key scaling challenges and device design requirements for high performance planar CMOS transistors below 50nm gate lengths. It finds that a nitrided gate oxide can scale to 50nm with gate leakage up to 100A/cm2. Mobility will be limited by channel impurity scattering below 35nm. Junction edge leakage limits channel doping. Source-drain extensions must be more abrupt to maintain parasitic resistance scaling below 35nm, requiring a non-equilibrium formation process and lateral abruptn

Author

Swati Matta

Language

EN