About this document
SoC Implementation Planning at 40nm by Student is a document available to read on EtoBox.
The document discusses guidelines for floorplanning large system-on-chip designs at the 40nm technology node. It covers creating an initial floorplan from physical architecture considerations, block placement guidelines, handling special blocks, and pushing block-level floorplans up from the top-level floorplan. The document provides detailed recommendations for each stage of floorplanning a large SoC design.
- Author
- Student
- Language
- EN