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Verilog Combinational Logic Synthesis by Raja Shekar is a document available to read on EtoBox.

What is Verilog Combinational Logic Synthesis about?

The document discusses various styles for synthesizing combinational logic in Verilog including gate netlists, continuous assignments, behavioral statements, functions, and tasks. It also covers synthesizing multiplexors, avoiding unwanted latches, priority logic, and sequential logic like shift registers and counters. Key points are synthesizable logic should not have feedback or timing constructs, and sequential logic is inferred when variables are assigned synchronously to edges.

Author

Raja Shekar

Language

EN