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This document provides instructions for Lab 1 of the ECE 3450: Digital Electronics course. The objectives of the lab are to develop a small cell library for datapath design by designing logic gates such as NOT, AND, OR, XOR, flip-flops and their layouts. Students must complete the lab independently, but can discuss course material. The submission must follow a specific naming convention and file organization for automated processing. A typical VLSI CAD flow is described including design entry, logic synthes

Author

BiloKhan

Language

EN