About this document
VLSI Clock Push and Pull Overview by maniroop is a document available to read on EtoBox.
To start a floor plan, the key inputs needed are the netlist (.v), library (.lib), LEF, and SDC files. The netlist contains the design hierarchy and connectivity. The library file contains cell timing, power, and functionality information. The LEF file contains physical details of the design like metal layers and cell pins. The SDC file defines clocks and timing constraints. During floor planning, macros are placed around the chip periphery while considering connections and reserving space. Congestion can o
- Author
- maniroop
- Language
- EN