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This paper presents a novel 20-transistor (20T) hybrid full adder designed for low power and high-performance computing using 45nm CMOS technology. The design integrates complementary and pass-transistor logic to achieve significant reductions in power consumption and propagation delay compared to traditional full adders. Simulation results demonstrate its suitability for energy-efficient arithmetic operations in digital systems, making it ideal for modern VLSI applications.
- Author
- i258520
- Language
- EN