About this scholarly article

Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06) - Evaluation time estimation for pass transistor logic circuits by Prasad, P.W.C.; Mills, B.I.; Assi, A.; Raseen, M.; Senanayake, S.M.N.A.; Prasad, V.C. is a scholarly article available to read on EtoBox.

Author

Prasad, P.W.C.; Mills, B.I.; Assi, A.; Raseen, M.; Senanayake, S.M.N.A.; Prasad, V.C.

Publisher

IEEE

Published

2006