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This document presents circuit techniques for a 3T gain cell embedded DRAM (eDRAM) that enhances data retention time and read speed while operating under low voltage conditions. The proposed design utilizes preferential boosting and a regulated bit-line write scheme to improve performance and reduce power dissipation. Simulation results from a 64 kb eDRAM test chip demonstrate significant improvements in retention time and speed compared to conventional designs.

Author

zhilianh02

Language

EN