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SystemVerilog-UVM TestBench Architecture by grspoorthy48 is a document available to read on EtoBox.

This paper presents a new UVM-based verification environment utilizing a SystemC golden functional reference model to enhance the simulation speed of VLSI chip design verification. The proposed architecture achieves up to 15 times faster simulation compared to traditional SystemVerilog-based models by leveraging Transaction Level Modeling (TLM) for communication. The methodology is validated through the verification of the execution unit of the RISC-V based VeeR EL2 processor core.

Author

grspoorthy48

Language

EN