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What is BIST Power Droop Reduction Method about?
This document proposes a novel scalable approach to reduce power droop during at-speed testing of sequential circuits using scan-based logic BIST. It aims to reduce power droop by decreasing the activity factor of the circuit under test through proper modification of the test vectors generated by the BIST. The approach reduces the number of flip flop outputs switching when new test vectors are applied, lowering power droop. It provides power droop reduction similar to normal circuit operation without increa
- Author
- RatnakarVarun
- Language
- EN