About this document
Vedic Math-Based High-Speed Arithmetic Unit by sara is a document available to read on EtoBox.
This document describes a proposed design for an arithmetic unit using techniques from Vedic mathematics to improve performance. Key points: - The design proposes a 32x32 bit arithmetic unit with two 32 bit inputs (A and B). - The main sections are a multiplier unit using the Vedic Urdhva Tiryagbhyam algorithm, carry save adders, an adder/subtractor, and a multiply-accumulate (MAC) unit. - The goal is to reduce computation time, area usage, and power consumption compared to traditional arithmetic unit
- Author
- sara
- Language
- EN