About this document
Congestion Optimization in VLSI Design by Jagadeep Kumar is a document available to read on EtoBox.
The document discusses congestion-driven placement techniques for VLSI standard cell design, emphasizing the importance of reducing interconnect congestion to improve circuit performance. It presents various placement algorithms and optimization methods, along with experimental results demonstrating significant congestion reduction and wire length management. The findings suggest that applying congestion reduction techniques at the flat level is more effective than within hierarchical levels.
- Author
- Jagadeep Kumar
- Language
- EN