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Design Exploration of Hybrid Caches with Disparate Memory Technologies by Xiaoxia Wu; Jian Li; Lixin Zhang; Evan Speight; Ram Rajamony; Yuan Xie is a Computer Science article available to read on EtoBox.

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Traditional multilevel SRAM-based cache hierarchies, especially in the context of chip multiprocessors (CMPs), present many challenges in area requirements, core--to--cache balance, power consumption, and design complexity. New advancements in technology enable caches to be built from other technologies, such as Embedded DRAM (EDRAM), Magnetic RAM (MRAM), and Phase-change RAM (PRAM), in both 2D chips or 3D stacked chips. Caches fabricated in these technologies offer dramatically different power-performance characteristics when compared with SRAM-based caches, particularly in the areas of access latency, cell density, and overall power consumption. In this article, we propose to take advantage of the best characteristics that each technology has to offer through the use of Hybrid Cache Architecture (HCA) designs. We discuss and evaluate two types of hybrid cache architectures: intercache-Level HCA (LHCA), in which the levels in a cache hierarchy can be made of disparate memory technologies; and intracache-level or cache-Region-based HCA (RHCA), where a single level of cache can be partitioned into multiple regions, each of a different memory technology. We have studied a number of d

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Author

Xiaoxia Wu; Jian Li; Lixin Zhang; Evan Speight; Ram Rajamony; Yuan Xie

Publisher

ACM

Published

2010

Language

EN

Field

Computer Science (Physical Sciences)