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2.4-3.0GHz Sub-Sampling PLL Design by 張智翔 is a document available to read on EtoBox.

This document presents a 2.4-3.0GHz process-tolerant sub-sampling phase-locked loop (SSPLL) with loop bandwidth calibration, designed to reduce loop gain deviations caused by process variations. The SSPLL, fabricated in a 40 nm CMOS process, achieves a power consumption of 5.81mW and demonstrates excellent phase noise performance with a measured rms jitter of 2.02ps at 3.0GHz. Key techniques include a gain calibration circuit and a pulse width control circuit to maintain a constant loop bandwidth despite va

Author

張智翔

Language

EN