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This paper proposes an improved lifting-based 3D discrete wavelet transform (DWT) VLSI architecture using a 9/7 filter. The architecture optimizes for efficient pipelining and parallelism to increase speed and hardware utilization. It uses a cascade of three 1D DWTs with memory buffers in between. Lifting-based DWT has advantages over traditional convolution-based implementations like lower complexity and regular data flow, making it suitable for VLSI. It breaks filters into upper and lower triangular matri

Author

Chandra Sekhar Tunga

Language

EN