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About this Engineering article
Planar normally-off GaAs JFET for high speed logic circuits by Kato, Y.; Dohsen, M.; Kasahara, J.; Taira, K.; Watanabe, N. is a Engineering article available to read on EtoBox.
It is typically read by researchers, students, and practitioners in Engineering.
- Author
- Kato, Y.; Dohsen, M.; Kasahara, J.; Taira, K.; Watanabe, N.
- Publisher
- The Institution of Electrical Engineers; Institution of Electrical Engineers; Institute of Electrical Engineers; Institution of Engineering and Technology (IET) (ISSN 0013-5194)
- Published
- 1981
- Field
- Engineering (Physical Sciences)
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