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Efficient Multi-Stage CMOS Rectifier Design by Manpreet Singh is a document available to read on EtoBox.
What is Efficient Multi-Stage CMOS Rectifier Design about?
The document presents a design for a multi-stage CMOS rectifier for UHF RFID tags to improve power efficiency. It proposes an analytical approach and design rules for multi-stage rectifiers that provide tradeoffs to maximize power efficiency. As an example, three-stage rectifiers are designed using a 90nm CMOS process that show 73% power efficiency and 55% lower power-up threshold compared to existing designs, allowing for longer operating range.
- Author
- Manpreet Singh
- Language
- EN